retro-silicon rebuilds classic consoles and computers chip by chip, in FPGA logic, as an open library of parts that can be reused from one system to the next: a 6502 here becomes the 6502 there. Every part is checked in simulation against a reference emulator and then on real FPGA boards, and the results on this site come straight from those runs. The work starts with the Nintendo Entertainment System and moves forward from there.
The NES runs on an AMD Zynq-7020, on a TUL PYNQ-Z2, built entirely with the open-source openXC7 toolchain, and every test gives the Tang boards’ CRCs: nestest, the save-state round trip, all 42 PPU test ROMs, and …
The NES’s picture now goes out over HDMI at 720p: three times its size, centred, with the console kept in step with the display so each display frame shows one NES frame whole. On the Tang Nano 20K a checksum of …
The NES now runs on a second board, the Sipeed Tang Console 138K, with its memory in block RAM, and every test gives the same CRCs as on the Tang Nano 20K: nestest 0xebba51ce, and all 42 PPU test ROMs with …
The picture processor, video/ppu-2c02, draws its first frames on the board, and they match the reference emulator exactly. Its timing follows MesenCE’s, so a frame from the core and a frame from MesenCE can be …
The NES’s CPU core, cpu/6502, matches the original chip on every bus access. In simulation it ran in lockstep with perfect6502, a transistor-level model of the real 6502, over two million cycles of random code with …